1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a structure of a nonvolatile memory capable of writing and erasing electrical information, that is, so called EEPROM (Electrical Erasable and Programmable Read Only Memory).
2. Description of the Prior Art
FIG. 1 is a block diagram showing an overall arrangement of an EEPROM.
Referring to FIG. 1, the EEPROM includes a memory array 50 formed of a plurality of EEPROM cells, a row address buffer 51 and a column address buffer 52 which receive externally applied row address signals and externally applied column address signals, respectively. The EEPROM also includes a row decoder 53 and a column decoder 54. The row decoder 53 decodes the address output from the row address buffer 51 and activates a word line coupled to a particular memory cell to be selected in the memory array while the column decoder 54 decodes the address output from the column address buffer 52 to activate a Y gate to connect a bit line coupled to the particular memory cell to I/0 line. A sense amplifier 56 senses via a Y gate 55 a data signal stored in the memory cell which has been selected by the row and column decoders. The sensed signal is amplified in the sense amplifier and fed out through an output buffer 57. Included also in the EEPROM is an input buffer 58 for providing control signals to various circuits associated with the memory array.
In FIG. 2, there is shown a schematic circuit diagram of the memory array and Y gate of FIG. 1.
Referring to FIG. 2, the Y gate 55 comprises a transistor 38 connected between an I/O line 40 and bit line 4, and a transistor 39 connected between the CG line 41 and a control gate line 35. To the gates of these transistors 38 and 39, a Y gate signal Y2 is supplied. A similar transistor arrangement is provided for a Y gate signal Y1.
In the configuration of the memory cell array of FIG. 2, only four memory cells are shown for storing four bits of data. Each memory cell comprises a floating gate transistor TR1 having a floating gate, and a select gate transistor TR2 for transferring a data signal stored in the floating gate transistor TR1 to a bit line 4. The gate of the select gate transistor TR2 is coupled to a word line 3. Another select gate transistor 34 is provided to transfer a signal on the control gate line 35 to the gate of the floating gate transistor TR1. The gate of the select gate transistor 34 is coupled to the word line 3.
To briefly describe the operation, the floating gate transistor TR1 is capable of taking two different storage or logic states depending on whether electrons are accumulated on its floating gate or not. When electrons are injected into the floating gate of the transistor TR1, the threshold voltage of the transistor shifts high, and therefore the transistor is non-conductive during read-out operation. This condition is defined as a logic "1" state. On the other hand, when electrons are removed from the floating gate, the threshold voltage of transistor TR1 shifts low, and the transistor TR1 is conducting during the read-out operation. This condition is defined as a logic "0" state.
The sense amplifier provides a read-out voltage to the bit line 4 via the transistor 38. From the bit line 4, the read-out voltage is fed to the floating gate transistor TR1 through the transistor TR2. This enables the sense amplifier to detect whether the current flows through the transistor TR1 or not, that is, to read the stored data of the floating gate transistor TR1.
FIG. 3A is a plan view showing a conventional EEPROM having a floating gate. FIG. 3B is a sectional view taken along the line IIIB--IIIB of FIG. 3A. Referring to FIGS. 3A and 3B, a description is made of a structure of the EEPROM.
The EEPROM comprises a floating gate transistor TR1 and a select gate transistor TR2 formed on a main surface of a silicon semiconductor substrate 11. The floating gate transistor TR1 comprises a drain region 8 and a source region 9 both formed on the main surface of the semiconductor substrate 11, a thin tunnel oxide film 6 formed on a predetermined region of the drain region 8, a floating gate 2 formed of polysilicon through an insulating film on a region of the semiconductor substrate 11 comprising at least the tunnel oxide film 6, and a control gate 17 formed on the floating gate 2 through an insulating film. The control gate 17 and the floating gate 2 form capacitance in an overlapping region with each other using the insulating film therebetween (an interlayer insulating film) as a dielectric material. The floating gate 2 and the drain region 8 form capacitance in a region in which the tunnel oxide film 6 is formed using the tunnel oxide film 6 as a dielectric material. In addition, the floating gate 2 and the semiconductor substrate 11 also form capacitance in a region other than the tunnel oxide film 6.
The floating gate 2 stores an electric charge. A discharge/charge of an electric charge is carried out between the floating gate 2 and the drain region 8 through the tunnel oxide film 6 in response to a voltage applied between the control gate 17 and the drain region 8.
The select gate transistor TR2 comprises the source region 8 (also used as the drain region of the floating gate transistor) and a drain region 12 both formed on the main surface of the semiconductor substrate 11, and a gate electrode 3 serving as a word line. The drain region 12 is connected to a bit line 4 through a contact hole 5.
The select gate transistor TR2 is turned on and off in response to a signal applied through a word line 3, whereby information of the floating gate transistor TR1 connected to the select transistor TR2 is read on the bit line 4. In addition, one cell of EEPROM including TR1 and TR2 is electrically insulated from adjacent cells by a region 10 for isolating devices.
Now, a description is made of operation of the EEPROM. EEPROM has three basic operational modes, i.e., Read, Erase and Write.
The following table shows the potentials which are applied to the various elements of the device herein described in order to read, erase and write any charge on floating gate 2. The various potentials shown under the columns entitled "READ" "ERASE" and "WRITE" are applied to those elements shown under the column entitles "ELEMENT" in the following table:
______________________________________ ELEMENT READ ERASE WRITE ______________________________________ Select gate 3 5 V V.sub.pp V.sub.pp Control gate 17 0 V V.sub.pp 0 Bit line 4 2 V 0 V V.sub.pp Source line 9 0 V 0 V Floating Floating gate 2 V.sub.F V.sub.E V.sub.W ______________________________________
where V.sub.pp is a program voltage, V.sub.F is a potential of the floating gate and V.sub.W and V.sub.E are potentials of the floating gate during each operation.
Thus, a shown in the above table, "to read" the device, that is, to determine whether the cell is in a high or low threshold state, 5 volts is placed on select gate 3, and 2 volts is placed on bit line 4, while control gate 17 and source line are placed at 0 volt. To "erase" the device, V.sub.pp is applied to the select gate 3 and the control gate 17, while the bit line 4 is maintained at 0 volt. This erase cycle will place a negative charge on the floating gate 2. To "write" the device, V.sub.pp is applied to the select gate and the bit line and 0 volt is applied to the control gate 17. This places positive charge on the floating gate 2.
FIG. 4A is an equivalent circuit diagram of the EEPROM shown in FIGS. 3A and 3B. Reference character C.sub.1 is tunnel capacitance formed in a tunnel region. Reference character C.sub.2 is capacitance formed by the floating gate 2, the control gate 17 and an insulating film therebetween. Reference character C.sub.3 is stray capacitance which is formed by the floating gate 2 other than the tunnel region, the drain region 8 formed under the floating gate 2 and an insulating film therebetween. For example, an equivalent circuit during ERASE MODE is shown in FIG. 4B. At this time, a potential V.sub.F at a point F is represented by the following equation; ##EQU1## where ##EQU2## is referred to as a coupling ratio, which is normally approximately 0.7.
An electric field of the tunnel insulating film and an amount of current flowing through the tunnel insulating film are represented by the following equations; ##EQU3## EQU J=A EOX.sup.2 exp (B/Eox) (3)
where Eox is an electric field, Tox is a thickness of the tunnel insulating film, J is a current, and A and B are constants. If the equation (2) is substituted in the equation (1) assuming that the coupling ratio is 0.7 and Tox is 10 nm, the following equation, EQU Eox=14 MV/cm
can be obtained. If this value is substituted in the equation (3), J becomes a sufficiently large value.
The above description is a summary of the conventional EEPROM.
Recently, computers have become of increased speed and capacity. Accordingly, an EEPROM has come to be demanded which is capable of being easily programmed and being highly integrated.
However, in order to integrate the EEPROM with a high density, the following problems must be solved. One of them is that the coupling ratio of the floating gate and the control gate needs to be kept above a constant value and another problem is that a area for the select gate transistor need to be reserved.
In order to solve these problems, the following measures have been conventionally taken. First, in order
to reduce the area for the select transistor V.sub.pp is lowered. If the V.sub.pp is lowered, a cut off voltage of the select transistor can be reduced. As a result, the select transistor becomes small. However, as described above, in order to obtain a sufficient tunnel current, the capacitance ratio needs to be raised as much as needed for that.
Another method is to make the area for the tunnel region small in order to make the capacitance ratio requirement. More specifically, if C.sub.1 becomes small, the denominator of the capacitance ratio becomes small and if C.sub.2 is the same, the capacitance ratio becomes bigger. In this case, C.sub.3 becomes large by an amount C.sub.1 is reduced. However, capacitance is proportional to a facing area of electrodes and it is inversely proportional to a thickness of the insulating film therebetween. The thickness of the insulating film of C.sub.1 is much smaller than that of C.sub.3. Accordingly, the ratio of a change of C.sub.1 is bigger than that of C.sub.3. As a result, if the tunnel region is made small, the capacitance ratio becomes large. Besides the above description, various efforts have been made to raise the degree of integration. For example, there is the above described method in which C.sub.2 is made large to raise the capacitance ratio. As a result, a highly integrated EEPROM described in U.S. Pat. No. 4,513,397 was invented.
FIG. 5A is a plan view showing the EEPROM disclosed in U.S. Pat. No. 4,513,397. FIG. 5B is a sectional view taken along a line VB--VB in FIG. 5A. FIG. 5C is a diagram showing an arrangement of memory cells of the EEPROM.
Referring to FIGS. 5A and 5B, a description is made of the EEPROM in which conventional writing/erasing characteristics have been improved. The conventional EEPROM is formed in a p well 31 formed on an n type substrate 11. The EEPROM comprises a first polysilicon layer 15 serving as a first control gate, a second polysilicon layer 2 serving as a floating gate formed thereon through an insulating film 24 and having one portion thereof extending over the first polysilicon layer, a third polysilicon layer 16 serving as a second control gate formed on the second polysilicon layer through an insulating film 27, n.sup.+ diffused layers 9 and 12 serving as a source and drain formed in the p well, and a field oxide film 10 for isolating elements.
When electrons are introduced to the floating gate, a constant voltage is applied to the control gates 15 and 16 with respect to the p well 31. As a result, electrons are introduced to the floating gate through a tunnel region 14. When electrons are drawn from the floating gate, a constant voltage is applied to the p well 31 with respect to the control gate 15 and 16. As a result, electrons are drawn to the drain 12 through the tunnel region 14. Electrons in the floating gate are read by applying a constant voltage to the control gates 15 and 16.
The conventional arrangement of EEPROM memory cells is shown in FIG. 5C. As can be seen from the figure, the second control gate serves as a word line in the conventional EEPROM.
In the conventional improved EEPROM, as previously stated, the value of C.sub.2 is increased by forming the control gate of the first polysilicon 15 and the third polysilicon 16. As a result, a high degree of integration is attained to some extent and writing/erasing characteristic have been improved.
However, the conventional improved EEPROM eliminated a select transistor for the purpose of a high degree of integration. This EEPROM is divided with a well at every cell or every byte to select a cell at every well. As a result, in the conventional EEPROM, electrons are introduced or drawn between the floating gate 2 and the substrate 11. Therefore, it is necessary to apply a high voltage to the substrate to draw electrons.
FIG. 6A is a plan view showing a p well formed on an n type substrate and 6B is a cross sectional view taken along a line VIB--VIB in FIG. 6A. Referring to the figures, when the p well is formed on the n type substrate general, the depth of the well d is 4 to 5 .mu.m. Therefore, a p type region extends also in a horizontal direction (a plane direction) by 3 to 4 .mu.m. Therefore, a wide isolation region of approximately 8 to 10 .mu.m is needed in order to electrically isolate the plurality of p wells. The more the bytes exist, the larger area necessary for isolation between p wells becomes. Therefore, a high degree of integration is not possible in the structured EEPROM.